On an optical disc, a groove that waves at a constant frequency is carved on a track, and an optical disc device can calculates an absolute address on the optical disc by counting waves (wobbles) of the groove even in a state where sectors are not allocated on the optical disc. Further, in a common optical disc device, rotation of an optical disc is controlled with reference to a wobble signal obtained from wobbles.
FIG. 6 is a block diagram illustrating a simplified construction of a conventional optical disc device that is disclosed in, for example, Japanese Published Patent Application No.Hei.11-16295. The optical disc device shown in FIG. 6 is provided with an optical pickup 2, a spindle motor 3, a wobble signal detector 4, a first PLL circuit 5, a control circuit 6, a reproduction signal detector 7, and a second PLL circuit 8.
The wobble signal detector 4 takes a wobble signal from an output signal of the optical pickup 2. The first PLL (Phase Locked Loop) circuit 5 receives a wobble signal S101 outputted from the wobble signal detector 4, and generates a wobble reference signal S104 that is synchronized with the wobble signal S101. The control circuit 6 controls the spindle motor 3 which rotates the optical disc 1 so that the frequency and phase of the wobble reference signal S104 take predetermined values.
The reproduction signal detector 7 takes a reproduction signal (analog signal) from data recorded on the optical disc 1, binarizes the reproduction signal to generate an RF envelope signal S110, and outputs the RF envelope signal S110 to a demodulator (not shown). Further, when it is detected from the reproduction signal that there is a blemish on the optical disc 1, the reproduction signal detector 7 outputs a blemish detection signal S118 to the second PLL circuit 8. The second PLL circuit 8 generates a data sync clock S103 using the RF envelope signal S110. The data sync clock S103 is input to the demodulator as an operation clock. Hereinafter, the construction and operation of the second PLL circuit 8 will be described in detail with reference to FIG. 7.
As shown in FIG. 7, the second PLL circuit 8 is provided with a charge pump controller 801, a charge pump 802, a filter 803, and a VCO (Voltage-Controlled Oscillator) 804. The charge pump controller 801 outputs a charge pump control signal S201 for controlling the charge pump 802, on the basis of the RF envelope signal S110 and the data sync clock S103 outputted from the VCO 804. The charge pump 802 outputs a first VCO control signal S202 that determines an oscillation frequency of the VCO 804, on the basis of the charge pump control signal S201. The filter 803 removes, from the first VCO control signal S202, noise components that are not needed for oscillation of the VCO, and outputs a second VCO control signal S203. The VCO 804 outputs the data sync clock S103 having an oscillation frequency corresponding to the second VCO control signal S203. Through the above-mentioned operation, the second PLL circuit 8 can output the data sync clock S103 whose phase and frequency are matched to the phase and frequency of the RF envelope signal S110. On the other hand, when the charge pump controller 801 receives the blemish detection signal S118 from the reproduction signal detector 7, the charge pump controller 801 generates a charge pump control signal S201 on the basis of only the data sync clock S103 outputted from the VCO8, and outputs it to the charge pump 802. Thereby, the second PLL circuit 8 goes into the hold state, and it can output the data sync clock S103 while maintaining the state, without matching the phase and frequency of the data sync clock S103 to the phase and frequency of the RF envelope signal S110.